In the presence of initial disturbances such as phase and frequency steps, the optimal phase-locked loops (PLL) filter is known to have time varying form. Typical PLL filter designs based on frequency response techniques cannot handle time varying filters and hence generate sub-optimal results. It has been recognized for some time now that state space methods in general and Kalman filtering techniques in particular can be used to design and analyze synchronizers or PLL, such as surveyed in "Phase-Locked Loops," S. C. Gupta, Proceedings of the IEEE, vol. 63, no. 2, February 1975. More specifically, Kalman filtering theory enables us to derive optimal synchronizer structures for a given phase disturbance model, generate the time varying and steady state filter gain parameters, and calculate the time varying performance of the synchronizer. Usually, the filter gain parameters as well as the performance measure are found recursively using the Kalman recursions as described, for example, in "DPLL Bit Synchronizer With Rapid Acquisition Using Adaptive Kalman Filtering Techniques," P. F. Driessen, IEEE Transactions on Communications, vol. 42, no. 9, September 1994 and in "Modeling of A PRML Timing Loop As a Kalman Filter," G. S. Christiansen, GlobeCom '94, vol. 2, Nov. 28-Dec. 2, 1994.
An undesirable property of many discrete-time synchronizers is the inherent presence of loop delay, such as described in "Effect of Loop Delay on Stability of Discrete-Time PLL", J. W. M. Bergmans, IEEE Transactions on Communications, vol. 42, no. 4, April 1995, which not only makes the synchronizer less stable but also degrades the performance of the synchronizer. Moreover, conventional PLLs in magnetic recordings use lower signal-to-noise ratio (SNR) values and compensate for this loss by providing more coding and error correction coding (ECC). The typical PLL loop latency in present PRML read channels is about 15-25 cells.
FIG. 1, for example, illustrates a general system block diagram of a typical prior art PLL 10 (known as second order type II) used in most disk drives that use sampled detection. Typical PLL 10 comprises an analog-to-digital converter (A/D) 12 receiving an input analog signal 11. AID 12 is coupled to a phase detector 14 to detect an estimated phase error 15 in PLL 10. Estimated phase error 15 is provided as input to a proportional integral (PI) filter 29 comprising a first multiplier 16, a first accumulator 18, a second multiplier 30 and a first adder 22. Latency compensated phase error output 23 of PI filter 29 is then coupled to a second accumulator 24, also known as voltage controlled oscillator (VCO), that sums a phase component (alpha) from multiplier 30 and a delayed frequency component (beta) from a first accumulator 18 of PI filter 32. Second accumulator 24 provides as output a filtered phase error control signal 27 to drive a phase mixer 28.
As the signal to noise ratio (SNR) becomes lower, the phase error or jitter increases thereby degrading the PLL performance 10. Conventional designs of PLL such as PLL 10 focus on minimizing the latency in the PLL loop, and not on compensating the effect of latency. There is therefore an urgent need to optimize the PLL performance with respect to disturbance sources, and with respect to the loop latency.